Interconnect technology, such as contacts and vias, has become increasingly important for designing integrated circuits (ICs) (also referred to as chips). Interconnects are part of the back-end-of-the-line (BEOL) processing in multi-layered semiconductor devices. On-chip interconnect technology distributes clock and data signals as well as power and ground signals to various functional blocks in an IC. As the IC designs become smaller and more compact, the size, dimensions, materials, and positioning of interconnect structures become increasingly significant factors in overall performance.
As seen in FIG. 2, front end of line (FEOL) processing results in semiconductor components 20, such as transistor elements (e.g., gates), on a semiconductor substrate. Back end of line (BEOL) processing results in BEOL structures, such as contacts 22, and vias 24, 26, as well as conductive layers M1, M2, M3 including conductive traces.
The contact and via resistances become a growing concern as device dimensions continue to shrink, where they are a significant fraction of the total local line resistance. As such, the delay associated with the signals traveling through the contacts and vias becomes a significant portion of the overall delay of the local interconnection of the IC.
Modeling tools are used by IC designers to estimate the resistance properties of complex interconnect systems, including structures such as the contact and via. Conventional modeling tools perform high-level simulations using finite element method calculations for the interconnect structure. However, existing modeling tools measure models of the contacts and vias based on average resistivity, thus providing an incomplete assessment of the total resistance.
Another characteristic of existing modeling tools is their requirement to recreate a simulation environment for a different technology node. Since existing modeling tools conventionally extract coefficients from existing silicon data (i.e., the coefficients are dependent on the physical dimensions), it is difficult to skew and scale with physical dimensions because the coefficients are restricted to simulating the contacts and vias for only a specific technology node and specific dimensions.
Further, employing existing modeling tools to extract resistance results occurs late in the development cycle, because the actual silicon data is available towards the end of the development cycle. As a result, changes to designs based on the results from the modeling tools delay the development cycle.
For the foregoing reasons, there is a need for providing a more physical scalable and accurate model of contacts and vias earlier in the development cycle.